1. Field of the Invention
The present invention relates to an integrated circuit device in which power supply is controlled for individual functional modules in order to reduce power consumption, and saving and restoration of data in an internal register or the like is controlled.
2. Description of the Related Art
A conventional method of implementing a low-power system on a chip (SoC) is to stop the operation of a functional module in an idling state in order to reduce power consumption. Stopping the clock is known as a method of stopping the operation of a functional module. However, even when the operation of a functional module is stopped by stopping the clock, power is kept supplied to the functional module itself, so power loss by leakage current cannot be prevented. To reduce this power loss by leak current, a method of stopping power supply to a functional module has been invented. The state in which a functional module is rendered inoperative because power supply has been stopped is called a sleep state.
When the power supply is shut down, all information held in a circuit is lost. To allow a functional module to return from the sleep state and resume the operation from the state immediately before sleep, a circuit arrangement which can hold data required after the return even though the functional module is set in the sleep state and power supply is stopped is indispensable. Methods proposed as a circuit arrangement such as this are a method in which, of circuit elements forming a functional module, power is always supplied to circuit elements for holding necessary data, and only power supply to other circuit elements is stopped, and a method in which necessary data is saved in another memory block or the like.
FIG. 13 is a circuit diagram showing such prior art. Referring to FIG. 13, logic circuits LA, LB, and LC are connected to a power supply VDD via switches SWA, SWB, and SWC, respectively. A flip-flop FF1 is connected between the logic circuits LA and LB, and a flip-flop FF2 is connected between the logic circuits LB and LC. These flip-flops FF1 and FF2 are also connected to the power supply VDD. The logic circuits LA, LB, and LC are equivalent to combinational circuits, and the flip-flops FF1 and FF2 are equivalent to sequential circuits. Power is always supplied to the flip-flops FF1 and FF2 to hold data so that the operation can be resumed after sleep from a state immediately before that. On the other hand, supply of power from the power supply VDD to the logic circuits LA, LB, and LC is shut down by turning off the switches SWA, SWB, and SWC as needed in order to reduce the power consumption. This prior art which thus controls the power supply method has the advantage that data need not be saved because power is always supplied to the flip-flops FF1 and FF2. Therefore, it is of course unnecessary to secure a storage area for data saving. However, as is apparent from FIG. 13, lines from the power supply VDD must be separated to those connected to the switches SWA, SWB, and SWC (logic circuits LA, LB, and LC) and those connected to the flip-flops FF1 and FF2. This makes the circuit layout very complicated. Also, NAND gates or the like must be added before the flip-flops FF1 and FF2 in order to prevent short circuit current. This undesirably increases the number of gates.
Note that prior art similar to that shown in FIG. 13 is described in Stephen V. Kosonocky, Mike Immediato, Peter Cottrell, et al.:
“Enhanced Multi-Threshold (MTCMOS) Circuits Using Variable Well Bias”, Proceedings of the 2001 International Symposium on Low Power Electronics and Design pp. 165-169, 2001.
In addition, several techniques for data saving when power supply to a functional module is to be appropriately shut down in order to reduce the power consumption are proposed. In these prior art references, power supply to a functional module is entirely shut down after necessary data in the module is saved, unlike the above prior art in which only power supply to the logic circuits is shut down and power is always supplied to the flip-flops. Another prior art which also performs such data saving saves the contents of a memory in external storage (e.g., a hard disk) (Jpn. Pat. Appln. KOKAI Publication No. 2000-82014). This prior art is highly reliable because the use of a hard disk or the like suppresses errors in the data saving area. However, this method is not preferable because saving data to external storage device takes long time.
Still another prior art which performs data saving saves data of flip-flops in a ferroelectric memory (FRAM: Ferroelectric Random Access Memory) by using a scan chain (Jpn. Pat. Appln. KOKAI Publication No. 10-78836). This prior art can reduce leakage current during a standby operation and hence is suited to reducing the power consumption. However, this prior art is disadvantageous in cost because a process of generally embedding both logic circuit and the FRAM is necessary in fabrication.
When a volatile memory such as a DRAM is to be used as a data saving area instead of a nonvolatile memory such as the FRAM, even if the voltage supplied to the data saving area is set to a minimum voltage necessary to hold data in order to reduce the power consumption, it is preferable to suppress a decrease in reliability of the saved data caused by, e.g., a so-called soft error. A soft error is a phenomenon in which data held in a transistor is changed by electric charge generated by the influence of αrays or neutrons incident from the outside. The maximum electric charge amount generated by a rays or neutrons is about 15 to 150 fC. If the amount of electric charge held by a transistor is so large as not to be influenced by an electric charge of about 15 to 150 fC, no soft error occurs. To this end, however, the applied voltage to the circuit must be raised, and this means power consumption of circuits also increase.
In addition, the supply voltage for a transistor is lowered not only for low power consumption but also by recent process scaling. For example, the critical charge of a logic cell is reportedly about 10 fC in a 1.0-V operation in a 100-nm process (P. Shivakumar, D. Burger, et al.: “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic”, Intl. Conf. On Dependable System and Network, 2002). The critical charge is a charge amount with which data held by a transistor is lost if more electric charge is added. From the foregoing, a voltage 15 times the normal voltage must be applied to make the critical charge larger than the charge amount produced by neutrons. This indicates that it is practically impossible to avoid soft errors by raising the applied voltage since process scaling is presently advancing.
It is desirable to provide an integrated circuit device capable of flexibly controlling power supply for each functional module in order to reduce the power consumption, and capable of controlling saving and restoration of necessary data accordingly. It is more preferable to realize this apparatus at low cost without lowering the reliability of data saving.